IMP-Host interface flow diagrams
Flow diagrams showing the step-by-step hardware logic of the IMP-to-host and host-to-IMP message interface.
Wingfield, M., "IMP-Host interface flow diagrams", RFC 12, DOI 10.17487/RFC0012, August 1969, <https://www.rfc-editor.org/info/rfc12>.
@misc{rfc12,
series = {Request for Comments},
number = 12,
howpublished = {RFC 12},
publisher = {RFC Editor},
doi = {10.17487/RFC0012},
url = {https://www.rfc-editor.org/info/rfc12},
author = {M. Wingfield},
title = {{IMP-Host interface flow diagrams}},
pagetotal = 1,
year = 1969,
month = aug,
} RFC text
Network Working Group M. Wingfield
Request for Comments: 12 REVISED 26 August 1969
IMP-HOST INTERFACE FLOW DIAGRAMS
The following flow diagrams were extracted from the logic diagrams
provided in Appendix B of BBN Report No. 1822. These diagrams
indicate the logical sequence of hardware operations which occur
within the IMP-HOST interface. The logic names appearing in the
blocks correspond to the logic elements found in Appendix B.
IMP to HOST Message
+----------+
| Start |
| Input |
+----------+
|
V
+------------------------+
| LAST <--0; IMPERR <--0 |
| PAD <--0; IN REQST <--0|
| COUNTER <--0 |
+------------------------+ +---+
|<----------------- | B |
V +---+
+--------------+
| RFNIB <-- 1 |
+--------------+
|<--------------+
V |
/ \ |
/ \ |
/ THERE'S \ N |
\YOUR BIT /----------+
\=1 ? /
\ /
|
+------------------->V
| / \
+----+------+ N / \
| IMP ERROR |<------ / IMP \
| <--- 1 | \ READY /
+-----------+ \ ? /
\ /
| Y
V
/ \
/ \
+-----------+ Y / LAST \
| PAD <-- 1 |<-------\ IMP BIT /
+-----------+ \ =1? /
| \ / +---+
+------------------->|<-----------------| C |
V +---+
+-----------------------+
| PULSE SHIFT REG. | +---+
| INCREMENT COUNTER |------>| A |
| RFNTR <-- 0 | +---+
+-----------------------+
+---+ +---+
| C | | A |
+-+-+ +-+-+
^ |
| Y V
/ \ / \
/ \ N /WORD \
/ PAD=1 \ <--------/ LENGTH \
\ ? / \ =1 /
\ / \ ? /
\ / \ /
| N |
V V
+---+ +----------------------+
| B | | INREQST <--1 |
+---+ +----------------------+
|<-----------+
V |
/ \ |
/DATA \ |
/HAS BEEN \_N_____|
\ TAKEN /
\ ? /
\ /
V Y
+----------------------+
| INREQST <--0 |
+----------------------+
V
/ \
/ \ +------------+
/ LAST = 1\----------->| END OF |
\ ? / | MESSAGE |
\ / +------------+
\ / ^
| N |
V |
/ \ |
/ \ |
/ PAD = 1 \-------------------+
\ ? /
\ /
\ /
| N
V
+---+ +---------------------+
| B |<---------| CLEAR COUNTER |
+---+ +---------------------+
HOST TO IMP MESSAGE
+--------------+
| START OUTPUT |
+------+-------+
V
+------------------------+
| COUNTER <-- 1 |
| LSTWD <--0; BTAVL <--0 |
+-----------+------------+ +---+
|<--------------------| C |
V +---+
+-----------+------------+
| OUT REQST <-- 1 |
| CLEAR SHIFT REG. |
+-----------+------------+
+------------>|
| V
| / \
| N / \
|_______ / STROBE \
\DATA WORD/
\ =1 ?/
\ /
V Y
+------------+------------+
| LOAD SHIFT REGISTER |
| OUTREQST <-- 0 |
| COUNTER <-- 1 |
+-------------------------+
+---------->|
| V
| / \
| / \
|N / RFNBIT \
+----- \ = 1 /
\ ? / +----------+
\ / | | N
V Y | / \
+--------+--------+ V / \
| THERE'S YOUR |----------->/ RFNBIT \
| HOST BET <-- 1 | \ = 0 /
+-----------------+ \ ? /
\ /
| Y
+-+-+
| A |
+---+
+---+
| A |
+---+
V
+--------------+-------------+
| THERE'S YOUR HOST BIT <--0 |
| BTAVL <-- 0 |
+----------------------------+
V
/ \ / \
/ WORD\ Y / \ Y
/LENGTH -1\---------->/ LSTWD \---+
\ = 1 / \ = 1 / |
\ ? / \ ? / |
\ / \ / |
| N | N |
V | |
/ \ | |
/ WORD\ | V
________________ / LENGTH \ | +------------+
| \ = 1 / | | LIBIT <- 1 |
| \ ? / | +------------+
| \ / V |
| |<-----------------------<------+
| V
| +-----------------+
| | PUSH SHIFT REG. |
+-------------+ |INCREMENT COUNTER|
| LIBIT <-- 0 | +-----------------+
+-------------+ V
| +---+
| | B |
V +---+
/ \
/ \
/ LSTWD \ Y +-------------+
\ = 1 /--------------------------->| END OF |
\ ? / | MESSAGE |
\ / +-------------+
| N
V
+---+
| C |
+---+
[ This RFC was put into machine readable form for entry ]
[ into the online RFC archives by Lorrie Shiota]
AI ELI5
On this page
§1What the Diagrams Are
RFC 12, marked as revised, by M. Wingfield and dated 26 August 1969, has one sentence of explanation. The flow diagrams were extracted from the logic diagrams provided in Appendix B of BBN Report No. 1822. They show the logical sequence of hardware operations that occur within the IMP-HOST interface, and the logic names in the blocks match logic elements in that appendix.
The remainder of the document is two diagrams made of boxes, decisions and connector markers.
Someone redrew the wiring plan as flowcharts so it is easier to follow the order of events.
§2IMP to Host Message
The input flow starts by clearing the flags LAST, IMPERR, PAD and IN REQST and a counter, then sets RFNIB. It waits for the "there's your bit" signal and checks whether the IMP is ready; if it is not, IMP ERROR is set.
It then tests whether this is the last IMP bit, pulses the shift register and increments the counter. When the word length is reached, INREQST is raised until the data has been taken. The flow ends when LAST or PAD is set; otherwise the counter is cleared and the loop continues.
The flowchart says: wait for the next piece, check the sender is ready, take it, count it, and stop when the sender says it was the last.
§3Host to IMP Message
The output flow starts by setting a counter to 1 and clearing LSTWD and BTAVL. It raises OUT REQST and clears the shift register, then waits for the strobe that signals a data word. The word is loaded into the shift register and OUTREQST is cleared.
The flow then waits on RFNBIT, sets and clears the "there's your host bit" signal, and tests word length. On the last word LIBIT is set. Each pass pushes the shift register and increments the counter, until the last word has been sent and the message ends.
The other flowchart is the mirror image: the computer says it has a word ready, hands it over bit by bit, and marks the final word.